1. Field of the Invention
The present invention relates to a synchronous semiconductor device and an inspection system for synchronous semiconductor devices, and more particularly to a synchronous semiconductor device and an inspection system for synchronous semiconductor device, incorporating a function to effectively perform burn-in stress test for screening defective products.
2. Description of the Prior Art
Any residual ionized movable impurity in the oxide of a semiconductor device may lead in practice to a permanent defective such as degenerated capacity to voltage and short circuit between wirings due to the displacement of such impurity caused by thermal or electric stresses. In order to eliminate these potentially problematic devices as defectives from final products prior to shipping, a burn-in stress test is performed. The burn-in stress test consists of a screening test by applying thermal and electric stresses to the subject.
The burn-in stress test is performed on the synchronous semiconductors in a similar manner. The synchronous semiconductors execute its internal operation in synchronism with an external clock. In order to apply electric stresses to the inside device, the operation is to be configured at the rate of the external clock.
For example, in a synchronous dynamic random access memory (referred to as SDRAM herein below), electric stresses will be at maximum when a word line is selected and a voltage more risen to the power supply voltage is applied to the gate of a MOS transistor. In order to apply to the entire device some electrical stresses, the selected word line has to be sequentially changed. Although by the demand of high-speed operation in these days a next generation SDRAM has been developed which enables accelerated cyclic operation by performing a series of data accesses in one command input, the burn-in stress test is indispensable for such products.
The prior art technology with respect to the ordinary SDRAM will be described by referring to the controller circuit of word lines shown in FIG. 10, and operating waveforms in FIG. 11. In the art, a control command CMD and a precharging command PRE_CMD may be input synchronously at the rising edge of an external clock CLK. A latch 110, 110 in a command latch circuit 100, 100 accepts the external clock CLK at an input and at the other input the output from a NAND circuit 130, 130 that receives the commands CMD and PRE_CMD and the external clock CLK, CLK. When the external clock CLK, CLK goes to high if either the control command CMD or the precharging command PRE_CMD is high then this command status will be latched. A one-shot trigger circuit 120, 120 in the following stage will be triggered by the transition of the output of the latch 110, 110 to low when latching so as to output a low-level pulse signal having the width determined by a series of inverters of odd stages (only three stages shown in FIG. 10). The pulse signal means an internal active signal ACTV, or an internal precharge signal PRE, which will set and reset the activating signal WL of word lines by repeatedly setting and resetting the latch 210 in the controller circuit 200 alternately and in synchronism with the rising edge of the external clock CLK, CLK. When resetting, the word line next to the one currently selected will be selected such that electrical stress will be applied sequentially through the device thoroughly.
Another prior art technology with respect to the next generation SDRAM will be described by referring to a controller circuit of word lines shown in FIG. 12 and to operating waveforms shown in FIG. 13. In this prior art, a circuit block 100 identical to the command latch circuit 100, 100 shown in FIG. 10 is implemented so as to accept the control command CMD synchronously input at the rising edge of an external clock CLK. A following one-shot trigger circuit 120 at the next stage will output a predetermined pulse at low-level. This low-level pulse is an internal active signal ACTV, which will be input to the controller circuit 200 to output to the word line activating signal WL.
The internal active signal ACTV is also input to an internal timer circuit 300. The internal timer circuit 300 can be composed of inverters of even stages as shown in FIG. 12, and may be composed of any arrangements which measure the given time t1. When the given time t1 elapses, the circuit outputs a low-level pulse signal for an internal precharge signal PRE to reset the latch 210 in the controller circuit 200 to deactivate the word line activating signal WL. Since in this next generation SDRAM, one command input causes a series of data accesses to be performed, the internal precharge signal PRE will be automatically issued after elapsing the given time t1 configured by the internal timer circuit 300 based on the internal active signal ACTV.
The word line activating signal WL activates the word line corresponding to a row address selected by the circuit not shown in the figure to apply electric stress during the given time t1 configured by the internal timer circuit 300. At the end of the given time t1, the activated word line will be deactivated and a next word line will be set. Then the identical operation will be iteratively repeated at the rising edge of the external clock CLK in order to apply the electrical stress to the entire device.
However, in the ordinary SDRAM as stated above, the activated period and precharging period of a word line will be iteratively repeated in an alternate manner for each cycle of the external clock CLK. Thus the period of time in which the electrical stress is applied to the device after activation of the word line will be one half of the net testing period. This indicates that a test that can apply the electrical stress more effective than this percentage is not achievable and that any attempts to further saving time of test may fail.
In addition, the next generation SDRAM as described above is required to operate at the external clock CLK of high frequency, on the demand of accelerated operation. The given time t1 to be measured by the internal timer circuit 300 will then be set to a shorter period of time appropriate to the power of data accessing operation. In the burn-in stress test on the other hand, the maximum performance may not be achieved by the limitation in the testing environment and the like, thus in general the synchronous semiconductor device has enough margins to operate with respect to the frequency of the external clock CLK used in the test. This concludes that the electrical stress may not effectively applied because of the small duty rate in the given time t1 that the word lines are activated.